A 47 \,\times\, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS
A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing transmi...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2010-12, Vol.45 (12), p.2828-2837 |
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| container_end_page | 2837 |
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| container_issue | 12 |
| container_start_page | 2828 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 45 |
| creator | O'Mahony, Frank Jaussi, James E Kennedy, Joseph Balamurugan, Ganesh Mansuri, Mozhgan Roberts, Clark Shekhar, Sudip Mooney, R Casper, Bryan |
| description | A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing transmitter driver with a sensitive receiver sampler. The active silicon area is compressed by 64% relative to the C4 bumps using on-chip transmission line routing. A dense, top-side package connector and bridge enable both high off-chip interconnect density and low overall power by reducing equalization and deskew requirements. The interface also demonstrates fast power management for the I/O circuits. The receiver power can be reduced by 93% during standby and an integrated wake-up timer indicates that all lanes return reliably to active mode in |
| doi_str_mv | 10.1109/JSSC.2010.2076214 |
| format | Article |
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The interface operates at 470 Gb/s with an aggregate bit error ratio better than 2 ×10 -18 while consuming 1.4 mW/Gb/s and occupies 3.2 mm 2 active silicon area.</description><subject>Bandwidth</subject><subject>Driver circuits</subject><subject>I/O</subject><subject>Integrated circuit interconnections</subject><subject>interface</subject><subject>link</subject><subject>low area</subject><subject>low power</subject><subject>Power demand</subject><subject>power management</subject><subject>power states</subject><subject>Receivers</subject><subject>standby</subject><subject>transceiver</subject><subject>Transceivers</subject><subject>Transmitters</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2010</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEFLxDAQhYMoWFd_gHjJD9i2M2mStsel6rqyskIVPRRC0qRQaas0e_Hfb-sunuY9Zt7w-Ai5RYgQIY-fy7KIGEyWQSoZ8jMSoBBZiGnyeU4CAMzCnAFckivvvybLeYYBuV9RntJqWe3b3vlqSRHo2sSeYsRp_xH_6Vc96q5zHd0Mezc2una0HSgXdOhp8bIrr8lFozvvbk5zQd4fH96Kp3C7W2-K1Tasp45ZyJFpB8ZpizlzIC3XliUcgefW8sZoENLaHIRBkwJOKst1Mi8TaSSTyYLg8W89fns_ukb9jG2vx1-FoGYMasagZgzqhGHK3B0zrXPu_15I4FJkyQFVd1O1</recordid><startdate>201012</startdate><enddate>201012</enddate><creator>O'Mahony, Frank</creator><creator>Jaussi, James E</creator><creator>Kennedy, Joseph</creator><creator>Balamurugan, Ganesh</creator><creator>Mansuri, Mozhgan</creator><creator>Roberts, Clark</creator><creator>Shekhar, Sudip</creator><creator>Mooney, R</creator><creator>Casper, Bryan</creator><general>IEEE</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>201012</creationdate><title>A 47 \,\times\, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS</title><author>O'Mahony, Frank ; Jaussi, James E ; Kennedy, Joseph ; Balamurugan, Ganesh ; Mansuri, Mozhgan ; Roberts, Clark ; Shekhar, Sudip ; Mooney, R ; Casper, Bryan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1108-412ae0bead192e06d4ad2341049dd4fba056dd905b1b701d9089a349dd36b6263</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Bandwidth</topic><topic>Driver circuits</topic><topic>I/O</topic><topic>Integrated circuit interconnections</topic><topic>interface</topic><topic>link</topic><topic>low area</topic><topic>low power</topic><topic>Power demand</topic><topic>power management</topic><topic>power states</topic><topic>Receivers</topic><topic>standby</topic><topic>transceiver</topic><topic>Transceivers</topic><topic>Transmitters</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>O'Mahony, Frank</creatorcontrib><creatorcontrib>Jaussi, James E</creatorcontrib><creatorcontrib>Kennedy, Joseph</creatorcontrib><creatorcontrib>Balamurugan, Ganesh</creatorcontrib><creatorcontrib>Mansuri, Mozhgan</creatorcontrib><creatorcontrib>Roberts, Clark</creatorcontrib><creatorcontrib>Shekhar, Sudip</creatorcontrib><creatorcontrib>Mooney, R</creatorcontrib><creatorcontrib>Casper, Bryan</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>O'Mahony, Frank</au><au>Jaussi, James E</au><au>Kennedy, Joseph</au><au>Balamurugan, Ganesh</au><au>Mansuri, Mozhgan</au><au>Roberts, Clark</au><au>Shekhar, Sudip</au><au>Mooney, R</au><au>Casper, Bryan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 47 \,\times\, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2010-12</date><risdate>2010</risdate><volume>45</volume><issue>12</issue><spage>2828</spage><epage>2837</epage><pages>2828-2837</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing transmitter driver with a sensitive receiver sampler. The active silicon area is compressed by 64% relative to the C4 bumps using on-chip transmission line routing. A dense, top-side package connector and bridge enable both high off-chip interconnect density and low overall power by reducing equalization and deskew requirements. The interface also demonstrates fast power management for the I/O circuits. The receiver power can be reduced by 93% during standby and an integrated wake-up timer indicates that all lanes return reliably to active mode in <;5 ns. The interface operates at 470 Gb/s with an aggregate bit error ratio better than 2 ×10 -18 while consuming 1.4 mW/Gb/s and occupies 3.2 mm 2 active silicon area.</abstract><pub>IEEE</pub><doi>10.1109/JSSC.2010.2076214</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2010-12, Vol.45 (12), p.2828-2837 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_5604658 |
| source | IEEE Electronic Library (IEL) |
| subjects | Bandwidth Driver circuits I/O Integrated circuit interconnections interface link low area low power Power demand power management power states Receivers standby transceiver Transceivers Transmitters |
| title | A 47 \,\times\, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS |
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