A 47 \,\times\, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS

A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing transmitter driver with a sensitive receiver sampler. The active silicon area is compressed by 64% relative to the C4 bumps using on-chip transmission line routing. A dense, top-side package connector and bridge enable both high off-chip interconnect density and low overall power by reducing equalization and deskew requirements. The interface also demonstrates fast power management for the I/O circuits. The receiver power can be reduced by 93% during standby and an integrated wake-up timer indicates that all lanes return reliably to active mode in