A study of the relationship between on-chip power distribution network voltage noise, charge per clock cycle, on-chip decoupling capacitance and clock jitter in a 40-nm field programmable gate array test chip

As technology process nodes continue to shrink, the performance of nano-technology devices becomes increasingly dependent on power quality. With core logic voltage reduced to 0.9 V, 40-nm devices are more susceptible to on-chip power distribution network (PDN) voltage noise. On-chip PDN voltage nois...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hui Lee Teng, Shishuang Sun, Man On Wong, Boyle, Peter, Chee Seong Fong
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Jitter Noise Registers Switches System-on-a-chip Voltage measurement
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