A study of the relationship between on-chip power distribution network voltage noise, charge per clock cycle, on-chip decoupling capacitance and clock jitter in a 40-nm field programmable gate array test chip

As technology process nodes continue to shrink, the performance of nano-technology devices becomes increasingly dependent on power quality. With core logic voltage reduced to 0.9 V, 40-nm devices are more susceptible to on-chip power distribution network (PDN) voltage noise. On-chip PDN voltage noise increases jitter and reduces a circuit's timing margin, which may lead to performance failures due to timing violations. This paper presents a study of the relationship between on-chip PDN voltage noise, charge per clock cycle (Q CYCLE ), on-chip decoupling capacitance (ODC), and internal clock period jitter. This study investigates the impact of on-chip PDN voltage noise, generated by switching internal logic elements, on jitter performance using two Altera 40-nm field programmable gate array (FPGA) test chips. The results from this study can aid chip designers in optimizing power quality, thereby achieving error-free timing design goals.