A 10-b, 100-MS/s CMOS A/D converter

A 10-b, 100-MS/s CMOS A/D converter

A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-/spl mu/m CM...

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Veröffentlicht in:IEEE journal of solid-state circuits 1997-03, Vol.32 (3), p.302-311
Hauptverfasser: Kwang Young Kim, Kusayanagi, N., Abidi, A.A.
Format: Artikel
Sprache:eng
Schlagworte:
Bandwidth
Clocks
CMOS analog integrated circuits
CMOS technology
Dynamic range
Operational amplifiers
Pipeline processing
Prototypes
Quantization
Signal resolution
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Beschreibung
Zusammenfassung:A new architecture for a CMOS A/D converter overcomes many of the known problems in the parallel operation of multiple pipelined stages. The input signal is sampled in one channel, and after quantization to 4 b, the residue is distributed into many channels. A prototype implemented in 1-/spl mu/m CMOS achieves 60 dB signal-to-noise plus distortion ratio (SNDR) at low conversion rates, with a resolution bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz conversion rate, and the bandwidth remains the same.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.557627