Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures

Network-on-Chip (NoC), a new System-on-Chip paradigm, has been proposed as a solution to mitigate complex on-chip interconnection problems. NoC architectures are able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. Especially, custom NoC topologies are able to further increase application'sperformance due to their adaptiveness. In this paper, we present a systematic methodology for generating an energy efficient application-specific NoC architecture. The methodology framework consists of the following steps: 1) greedy application partitioning, 2) automatic topology generation and extensive exploration, and 3) an energy-aware router optimization so as to find the best architecture that meets applications requirements. Validation of the proposed framework was performed using four DSP/multimedia applications showing that energy-aware irregular NoCs can achieve on average 53% energy reduction, without violating applications timing constrains.