Test quality of asynchronous circuits: a defect-oriented evaluation

This paper investigates the test quality of asynchronous circuits using fault models that are grounded in realistic defect probabilities. As for synchronous designs, I/sub DDQ/ testing plays a prominent role in detecting CMOS manufacturing defects for asynchronous designs, too. However, for asynchronous circuits, I/sub DDQ/ testing is usually less effective because fewer states are quiescent, and our analysis shows that the test quality can only be improved by creating more quiescent states. We present a new Design-for-Test (DfT) method that provides good test quality in that all defects are detected that are likely to occur given the IC layout and process technology and that pose quality or reliability problems. Our DfT method is evaluated on three in-house manufactured designs.