The Design and Implementation of Repeater with Digital Predistortion

As the development of wireless communication technology, high-power and low-cost digital repeaters are applied more and more widely. But, under the constraint from non-linear characteristics of power amplifier (PA), the efficiency of repeater is greatly decreased. Thus, digital predistortion (DPD) algorithm and its implementation become hotspot in wireless technology research domain. This paper proposes one method to implement digital predistortion based on one FPGA chip, and gives its implementation solution. Simulation results show the method is simple and reliable, and can improve greatly the output power of repeater.