Notice of Violation of IEEE Publication Principles: Calculus-based runtime verification

A uniform calculus-based approach for synthesizing monitors checking correctness properties specified by a large variety of logics at runtime is provided, including future and past time logics, interval logics, state machine and parameterized temporal logics. Thus we can synthesize monitors from the logical specification in an uniform fashion to incrementally analysis the current execution traces during test and real run. The monitor detects both good and bad prefix of a particular kind, namely those that are informative for the property under investigation. Notice of Violation of IEEE Publication Principles "Calculus-based Runtime Verification" by Benzhai Hai, Fangfang Li, Ruiyun Xie, Yanhao Chen in the 2010 3rd IEEE International Conference on Computer Science and Information Technology (ICCSIT), 2010, pp. 271 - 275 After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles. This paper contains significant portions of original text from the paper cited below. The original text was copied with insufficient attribution (including appropriate references to the original author(s) and/or paper title) and without permission. Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article: "Calculus-based Runtime Verification" by Xuan Qi and Changzhi Zhao in the World Academy of Science, Engineering and Technology 58, 2009, pp. 278 - 282