Classification and benchmarking of III-V MOSFETs for CMOS

A classification scheme for III-V MOSFETs for future CMOS is proposed and n-channel devices are benchmarked both within the group of III-V MOSFETs and in comparison with state-of-the-art silicon MOSFETs. Metrics which are based on the first derivative of drain current (I d ) vs gate voltage (V gs ) are found to be most suitable for benchmarking technologies of widely diverging maturity level. Although recently reported III-V MOSFETs exhibit markedly improved performance, they still lag state-of the-art Si MOSFETs. However, Schottky gate III-V devices with an InAs channel layer already outperform silicon MOSFETs today.