Instructionless processor architecture using dynamically reconfigurable logic

Instructionless processor architecture using dynamically reconfigurable logic

In this paper the idea of the general-purpose processor implemented in dynamically reconfigurable FPGA is presented. The novelty of the proposed solution lays in the lack of typical sequential processing - all operations are realized in parallel in the hardware. At the same time the new architecture...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kielbik, Rafal, Jablonski, Grzegorz, Swiercz, Bartlomiej, Amrozik, P
Format: Tagungsbericht
Sprache:eng
Schlagworte:
dynamic reconfiguration
Field programmable gate arrays
FPGA
general-purpose processor
Hardware
Memory management
Operating systems
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Beschreibung
Zusammenfassung:In this paper the idea of the general-purpose processor implemented in dynamically reconfigurable FPGA is presented. The novelty of the proposed solution lays in the lack of typical sequential processing - all operations are realized in parallel in the hardware. At the same time the new architecture does not impose any modification of the software development process.