Efficient VLSI implementation of a finite field multiplier using reordered normal basis

A new VLSI implementation for a finite field multiplier using reordered normal basis is presented. The hardware architecture uses domino logic building blocks as well as True Single Phase Clock (TSPC) flip-flops to achieve exceptional performance. The multiplier has been realized in a 0.18 μm CMOS p...

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Bibliographische Detailangaben
Hauptverfasser:	Leboeuf, K, Namin, A H, Huapeng Wu, Muscedere, R, Ahmadi, M
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	binary field Clocks CMOS logic circuits CMOS process domino logic Finite field Flip-flops Galois fields Hardware hardware implementation multiplier NIST normal basis Public key cryptography Silicon Very large scale integration
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