Efficient VLSI implementation of a finite field multiplier using reordered normal basis

A new VLSI implementation for a finite field multiplier using reordered normal basis is presented. The hardware architecture uses domino logic building blocks as well as True Single Phase Clock (TSPC) flip-flops to achieve exceptional performance. The multiplier has been realized in a 0.18 μm CMOS process and can perform multiplication correctly up to a clock rate of 1.789 GHz, requiring 62048 μm 2 of silicon area. Compared to similar implementations, the new design yields a 43% reduction in area utilization, and a 12% increase in maximum operating speed. The size of the multiplier, 233, is recommended by the National Institute of Standard and Technology (NIST) for elliptic key cryptography. Finite field multipliers such as the proposed one have applications in public key cryptography for constrained devices such as smart cards or hand held devices.