A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter (ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital Converter (TDC) that is robust against process variation and suitable for embedding within a 3-bit ADC is discussed and...

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Bibliographische Detailangaben
Hauptverfasser: Townsend, K A, Macpherson, A R, Haslett, J W
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analog-digital conversion
Clocks
Delay effects
Delay lines
Radio frequency
Robustness
Sampling methods
Signal resolution
Tunable circuits and devices
Voltage
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Beschreibung
Zusammenfassung:This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter (ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital Converter (TDC) that is robust against process variation and suitable for embedding within a 3-bit ADC is discussed and its performance evaluated. Simulation shows that when the TDC is designed in a 90nm CMOS process it is capable of a DNL and INL less than ±0.040L5B and ±0.015LSB, respectively, for 9mW of power consumption at 5GS/s with a 6.25ps resolution.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2010.5538004