PWL cores for nonlinear array processing
This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broad...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 3316 |
|---|---|
| container_issue | |
| container_start_page | 3312 |
| container_title | |
| container_volume | |
| creator | Di Federico, M Julián, P Mandolesi, P S Andreou, A G |
| description | This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized. Based on a 90nm technology process, the different options will be analyzed and compared using simulations. |
| doi_str_mv | 10.1109/ISCAS.2010.5537906 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5537906</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5537906</ieee_id><sourcerecordid>5537906</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-fd135cdeb33be7369b9bbcc2f682edc4f0fda3a6a27cad4fa74feb84f845512b3</originalsourceid><addsrcrecordid>eNo1kM1KAzEYRT9_Co51XkA3s3STmnz5X5ahamFAoYrLkmQSGakzJXHTt7dgvZvD5cBdXIBbRheMUfuw3rTLzQLpsUvJtaXqDGqrDRMohOTU4jlUyKQhTKK8gOt_YewlVBQ1I4JTnEFlKFFCHc0V1KV80WOERMV1BfevH10TphxLk6bcjNO4G8bocuNydodmn6cQSxnGzxuYJbcrsT5xDu-Pq7f2mXQvT-t22ZGBaflDUs-4DH30nPuoubLeeh8CJmUw9kEkmnrHnXKog-tFclqk6I1IRkjJ0PM53P3tDjHG7T4P3y4ftqcD-C-B4Ui8</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>PWL cores for nonlinear array processing</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Di Federico, M ; Julián, P ; Mandolesi, P S ; Andreou, A G</creator><creatorcontrib>Di Federico, M ; Julián, P ; Mandolesi, P S ; Andreou, A G</creatorcontrib><description>This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized. Based on a 90nm technology process, the different options will be analyzed and compared using simulations.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 1424453089</identifier><identifier>ISBN: 9781424453085</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 9781424453092</identifier><identifier>EISBN: 1424453097</identifier><identifier>DOI: 10.1109/ISCAS.2010.5537906</identifier><identifier>LCCN: 80-646530</identifier><language>eng</language><publisher>IEEE</publisher><subject>Arithmetic ; Array signal processing ; Cellular neural networks ; CMOS technology ; Computational modeling ; Microprocessors ; Photodiodes ; Piecewise linear techniques ; Standards development ; Very large scale integration</subject><ispartof>2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.3312-3316</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5537906$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5537906$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Di Federico, M</creatorcontrib><creatorcontrib>Julián, P</creatorcontrib><creatorcontrib>Mandolesi, P S</creatorcontrib><creatorcontrib>Andreou, A G</creatorcontrib><title>PWL cores for nonlinear array processing</title><title>2010 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized. Based on a 90nm technology process, the different options will be analyzed and compared using simulations.</description><subject>Arithmetic</subject><subject>Array signal processing</subject><subject>Cellular neural networks</subject><subject>CMOS technology</subject><subject>Computational modeling</subject><subject>Microprocessors</subject><subject>Photodiodes</subject><subject>Piecewise linear techniques</subject><subject>Standards development</subject><subject>Very large scale integration</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424453089</isbn><isbn>9781424453085</isbn><isbn>9781424453092</isbn><isbn>1424453097</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kM1KAzEYRT9_Co51XkA3s3STmnz5X5ahamFAoYrLkmQSGakzJXHTt7dgvZvD5cBdXIBbRheMUfuw3rTLzQLpsUvJtaXqDGqrDRMohOTU4jlUyKQhTKK8gOt_YewlVBQ1I4JTnEFlKFFCHc0V1KV80WOERMV1BfevH10TphxLk6bcjNO4G8bocuNydodmn6cQSxnGzxuYJbcrsT5xDu-Pq7f2mXQvT-t22ZGBaflDUs-4DH30nPuoubLeeh8CJmUw9kEkmnrHnXKog-tFclqk6I1IRkjJ0PM53P3tDjHG7T4P3y4ftqcD-C-B4Ui8</recordid><startdate>201005</startdate><enddate>201005</enddate><creator>Di Federico, M</creator><creator>Julián, P</creator><creator>Mandolesi, P S</creator><creator>Andreou, A G</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201005</creationdate><title>PWL cores for nonlinear array processing</title><author>Di Federico, M ; Julián, P ; Mandolesi, P S ; Andreou, A G</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-fd135cdeb33be7369b9bbcc2f682edc4f0fda3a6a27cad4fa74feb84f845512b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Arithmetic</topic><topic>Array signal processing</topic><topic>Cellular neural networks</topic><topic>CMOS technology</topic><topic>Computational modeling</topic><topic>Microprocessors</topic><topic>Photodiodes</topic><topic>Piecewise linear techniques</topic><topic>Standards development</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Di Federico, M</creatorcontrib><creatorcontrib>Julián, P</creatorcontrib><creatorcontrib>Mandolesi, P S</creatorcontrib><creatorcontrib>Andreou, A G</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Di Federico, M</au><au>Julián, P</au><au>Mandolesi, P S</au><au>Andreou, A G</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>PWL cores for nonlinear array processing</atitle><btitle>2010 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2010-05</date><risdate>2010</risdate><spage>3312</spage><epage>3316</epage><pages>3312-3316</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424453089</isbn><isbn>9781424453085</isbn><eisbn>9781424453092</eisbn><eisbn>1424453097</eisbn><abstract>This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized. Based on a 90nm technology process, the different options will be analyzed and compared using simulations.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2010.5537906</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0271-4302 |
| ispartof | 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.3312-3316 |
| issn | 0271-4302 2158-1525 |
| language | eng |
| recordid | cdi_ieee_primary_5537906 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Arithmetic Array signal processing Cellular neural networks CMOS technology Computational modeling Microprocessors Photodiodes Piecewise linear techniques Standards development Very large scale integration |
| title | PWL cores for nonlinear array processing |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T12%3A11%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=PWL%20cores%20for%20nonlinear%20array%20processing&rft.btitle=2010%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Di%20Federico,%20M&rft.date=2010-05&rft.spage=3312&rft.epage=3316&rft.pages=3312-3316&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=1424453089&rft.isbn_list=9781424453085&rft_id=info:doi/10.1109/ISCAS.2010.5537906&rft_dat=%3Cieee_6IE%3E5537906%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424453092&rft.eisbn_list=1424453097&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5537906&rfr_iscdi=true |