PWL cores for nonlinear array processing

PWL cores for nonlinear array processing

This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broad...

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Hauptverfasser: Di Federico, M, Julián, P, Mandolesi, P S, Andreou, A G
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Arithmetic
Array signal processing
Cellular neural networks
CMOS technology
Computational modeling
Microprocessors
Photodiodes
Piecewise linear techniques
Standards development
Very large scale integration
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Beschreibung
Zusammenfassung:This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized. Based on a 90nm technology process, the different options will be analyzed and compared using simulations.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2010.5537906