Energy profile of a microcontroller for neural prosthetic application

A third-generation microcontroller has been designed to operate as a control element in an embedded wireless neural interface system. This design was fabricated in the IBM 65nm CMOS process. We present an analysis of the energy profile of the fabricated microcontroller by measuring the energy to execute each family of instructions. We also investigate the efficiency of new instructions for block transfers. Finally, we discuss implications of these results for energy-efficient operation. The fabricated chip is operational at up to 150MHz. With a core power supply of 0.8V, the chip consumes 350uW at 10MHz. The new block transfer instructions are as much as 44% more efficient than traditional load-store sequences for saving registers to memory, and up to 15% more efficient when transferring 16-byte chunks of data.