Energy-efficient time-interleaved and pipelined SAR ADCs

Energy-efficient time-interleaved and pipelined SAR ADCs

New architectures are proposed for the realization of micro-power analog-to-digital data converters. They are based on a time-interleaving and pipelining successive-approximation-register (SAR) structure. The resulting ADCs require very low power dissipation for medium-speed and medium-accuracy data...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Jiaming Lin, Wenhuan Yu, Temes, G C
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Analog-digital conversion
Biosensors
Capacitance
Capacitors
Clocks
Data conversion
Energy efficiency
Pipeline processing
Power dissipation
Voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:New architectures are proposed for the realization of micro-power analog-to-digital data converters. They are based on a time-interleaving and pipelining successive-approximation-register (SAR) structure. The resulting ADCs require very low power dissipation for medium-speed and medium-accuracy data conversion.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2010.5537328