Design of a 70-MHz IF 10-MHz bandwidth bandpass ΣΔ modulator for WCDMA applications

In this paper we present a MASH bandpass ΣΔ modulator for WCDMA applications. The signal bandwidth of the proposed modulator is 10 MHz, centered around an intermediate frequency (IF) of 70 MHz. Each ΣΔ modulator of the MASH structure is based on a two-path architecture, which allow us to obtain the desired in-band noise shaping zeros and reduce the power consumption. The ΣΔ modulator is implemented using a 0.18-nm CMOS technology and a sampling frequency of 180 MHz. The simulations at transistor level show a resolution of about 13 bits, with a bandwidth of 10 MHz, and a power consumption of about 90 mW, with a supply voltage of 1.8 V, resulting in a figure of merit (FoM BP ) as low as about 0.15 pJ/conversion-level.