Polysilicon source/drain thin film SOI MOSFET by using CMP technology

A thin film SOI MOSFET with a polysilicon source/drain was fabricated by using chemical mechanical polishing. The source/drain resistance was reduced as compared with that of the conventional MOSFET. The channel carrier mobility degradation caused by RIE damage, usually found in conventional polysilicon source/drain structures, was not observed in the proposed structure. On the fabrication process, an Si/sub 3/N/sub 4//SiO/sub 2/ stack under the CVD oxide acts as a protecting layer during the RIE process of the polysilicon and subsequent thermal oxidation of the polysilicon. Furthermore, since the source/drain was formed by the diffusion of impurities from the polysilicon, the sidewall dopant encroachment of this structure is much lower than that of those conventional structures, and as a result, the electrical performance of the resultant SOI MOSFET is enhanced.