Assembly and reliability of advanced packaging technologies in high speed networking applications

High end networking and computing applications continue to drive silicon technologies for higher data rates and increased bandwidth. The push for silicon performance with 45nm and 32nm devices also drives a need for packaging performance to deliver clean and efficient power to the device. This paper compares the electrical performance, assembly and reliability of various advanced packaging technologies, which are aimed to improve the DC and AC power delivery network (PDN) in a network ASIC (Application Specific Integrated Circuit). A baseline ASIC component was redesigned and fabricated into (1) a hybrid package placing the baseline ASIC onto a customized interposer board fabricated with both conventional and advanced high-capacitance laminate systems (2) a package utilizing a conventional substrate having capacitors interspersed between the BGA-balls, (3) a package utilizing an organic substrate with an embedded bulk array capacitor, and (4) a package using a coreless substrate. The bare substrates and ASIC component were assembled through conventional high volume processes whenever possible. The ASIC components were then assembled onto line cards using conventional board level assembly parameters and techniques. Electrical and reliability testing were performed at both device level and product level. For electrical measurement, improvements to the PDN were quantified by measuring the power rail noise and clock jitter and comparing each package variant to the performance of the baseline ASIC. The package design, signal routing, device, and system, assembly and test environments are essentially unchanged; the differences are attributed primarily to the substrate and package technology itself. A strong correlation between simulation results and electrical performance data was observed. A qualitative/quantitative system of comparing the cost, complexity and capability of each solution was used to evaluate their viability for implementation into high volume manufacturing. Package and Board Level Reliability (BLR) was conducted on the most viable solutions.