The challenges and limitations on triple level cell geometry and process beyond 20 nm NAND Flash technology

The challenges and limitations on triple level cell geometry and process beyond 20 nm NAND Flash technology

This paper investigates the challenges and difficulties of TLC cell geometry and process beyond 20nm NAND technology from the viewpoint of programmed V th level, new HCI disturbance and charge loss in the highest programmed level.

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Bibliographische Detailangaben
Hauptverfasser: Yunbong Lee, Byoungjun Park, DaeHwan Yun, YeonJoo Jeong, Pyoung Hwa Kim, Ji Yul Park, Hae Chang Yang, Myoung Kwan Cho, Kun-Ok Ahn, Yohwan Koh
Format: Tagungsbericht
Sprache:eng ; jpn
Schlagworte:
Boosting
Electron traps
Electronic mail
Flash memory
Geometry
Hot carrier injection
Human computer interaction
Leakage current
Substrate hot electron injection
Voltage
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Beschreibung
Zusammenfassung:This paper investigates the challenges and difficulties of TLC cell geometry and process beyond 20nm NAND technology from the viewpoint of programmed V th level, new HCI disturbance and charge loss in the highest programmed level.
ISSN:2159-483X
DOI:10.1109/IMW.2010.5488388