A study of barrier engineered Al2O3 and HfO2 high-K charge trapping devices (BE-MAONOS and BE-MHONOS) with optimal high-K thickness

The behavior of barrier engineered charge trapping devices incorporating Al 2 O 3 and HfO 2 high-K layers has been critically examined. We propose to use a thicker buffer oxide (≫ 6 nm) and thin (≪5nm) high-K top capping layer for BE-MAONOS and BE-MHONOS in order to improve the reliability. Thinner high-K top capping layer reduces the fast initial charge loss under high-temperature baking. Moreover, it also reduces the undesired transient read current relaxation. These effects are due to the bulk trapped charge in high-K material during programming/erasing. By reducing the high-K thickness these reliability issues can be minimized. We also found that HfO 2 has a better thickness scaling capability than Al 2 O 3 . Finally, a high-performance BE-SHONOS (with n + -poly gate and HfO 2 top capping layer) transistor is demonstrated in this work.