Power improvement for 65nm nMOSFET with high-tensile CESL and fast nonlinear behavior modeling

Power improvement for 65nm nMOSFET with high-tensile CESL and fast nonlinear behavior modeling

In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the...

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Hauptverfasser: Chia-Sung Chiu, Kun-Ming Chen, Guo-Wei Huang, Shu-Yu Lin, Bo-Yuan Chen, Cheng-Chou Hung, Sheng-Yi Huang, Cheng-Wen Fan, Chih-Yuh Tzeng, Sam Chou
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS technology
Contact etch stop layer (CESL)
Etching
MOSFET circuits
nMOSFET
Nonlinear distortion
Performance analysis
PHD
Power amplifiers
Predictive models
Semiconductor device modeling
Strain control
stress
Stress control
X-parameters
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Beschreibung
Zusammenfassung:In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the polyharmonic distortion (PHD) model extraction by X-parameters measurement when the power transistor was designed to work far from 50 ohms. By mean of this model, the accurate nonlinear behaviors of nMOSFET were obtained rapidly.
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2010.5477258