Leap frog multiplier

Array multipliers are popular due to their regular compact structure. Timing analysis of a full adder has resulted in a different array connection pattern that provides improved throughput for the multiplier while reducing its power dissipation from spurious transitions. The paper details the new ar...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Mahant-Shetti, S.S., Lemonds, C., Balsara, P.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Adders Circuits Delay Instruments Latches Pattern analysis Power dissipation Throughput Timing Topology
Online-Zugang:	Volltext bestellen
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