Leap frog multiplier

Leap frog multiplier

Array multipliers are popular due to their regular compact structure. Timing analysis of a full adder has resulted in a different array connection pattern that provides improved throughput for the multiplier while reducing its power dissipation from spurious transitions. The paper details the new ar...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Mahant-Shetti, S.S., Lemonds, C., Balsara, P.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Adders
Circuits
Delay
Instruments
Latches
Pattern analysis
Power dissipation
Throughput
Timing
Topology
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Beschreibung
Zusammenfassung:Array multipliers are popular due to their regular compact structure. Timing analysis of a full adder has resulted in a different array connection pattern that provides improved throughput for the multiplier while reducing its power dissipation from spurious transitions. The paper details the new array design and some results obtained.
DOI:10.1109/LPE.1996.547512