Floating body effects in partially-depleted SOI CMOS circuits
This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dyn...
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| creator | Lu, P.F. Ji, J. Chuang, C.T. Wagner, L.F. Hsieh, C.M. Kuang, J.B. Hsu, L. Pelella, M.M. Chu, S. |
| description | This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for. |
| doi_str_mv | 10.1109/LPE.1996.547496 |
| format | Conference Proceeding |
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The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.</description><identifier>ISBN: 0780335716</identifier><identifier>ISBN: 9780780335714</identifier><identifier>DOI: 10.1109/LPE.1996.547496</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit stability ; Circuit topology ; CMOS digital integrated circuits ; Degradation ; FETs ; Impact ionization ; MOSFET circuits ; Semiconductor device modeling ; Silicon ; Switching circuits</subject><ispartof>Proceedings of 1996 International Symposium on Low Power Electronics and Design, 1996, p.139-144</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/547496$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,4035,4036,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/547496$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lu, P.F.</creatorcontrib><creatorcontrib>Ji, J.</creatorcontrib><creatorcontrib>Chuang, C.T.</creatorcontrib><creatorcontrib>Wagner, L.F.</creatorcontrib><creatorcontrib>Hsieh, C.M.</creatorcontrib><creatorcontrib>Kuang, J.B.</creatorcontrib><creatorcontrib>Hsu, L.</creatorcontrib><creatorcontrib>Pelella, M.M.</creatorcontrib><creatorcontrib>Chu, S.</creatorcontrib><title>Floating body effects in partially-depleted SOI CMOS circuits</title><title>Proceedings of 1996 International Symposium on Low Power Electronics and Design</title><addtitle>LPE</addtitle><description>This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.</description><subject>Circuit stability</subject><subject>Circuit topology</subject><subject>CMOS digital integrated circuits</subject><subject>Degradation</subject><subject>FETs</subject><subject>Impact ionization</subject><subject>MOSFET circuits</subject><subject>Semiconductor device modeling</subject><subject>Silicon</subject><subject>Switching circuits</subject><isbn>0780335716</isbn><isbn>9780780335714</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jr0KwjAYAAMi-NdZcMoLtCamSc3gVCoKSoW6l9h-lUhsSxKHvr2Czt5ywy2H0JKSiFIi16dLFlEpRcTjJJZihGYk2RLGeELFBAXOPciHmPMNE1O025tOed3e8a2rBwxNA5V3WLe4V9ZrZcwQ1tAb8FDjIj_i9JwXuNK2emnvFmjcKOMg-HmOVvvsmh5CDQBlb_VT2aH8jrC_8Q0ChjZG</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Lu, P.F.</creator><creator>Ji, J.</creator><creator>Chuang, C.T.</creator><creator>Wagner, L.F.</creator><creator>Hsieh, C.M.</creator><creator>Kuang, J.B.</creator><creator>Hsu, L.</creator><creator>Pelella, M.M.</creator><creator>Chu, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1996</creationdate><title>Floating body effects in partially-depleted SOI CMOS circuits</title><author>Lu, P.F. ; Ji, J. ; Chuang, C.T. ; Wagner, L.F. ; Hsieh, C.M. ; Kuang, J.B. ; Hsu, L. ; Pelella, M.M. ; Chu, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_5474963</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Circuit stability</topic><topic>Circuit topology</topic><topic>CMOS digital integrated circuits</topic><topic>Degradation</topic><topic>FETs</topic><topic>Impact ionization</topic><topic>MOSFET circuits</topic><topic>Semiconductor device modeling</topic><topic>Silicon</topic><topic>Switching circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Lu, P.F.</creatorcontrib><creatorcontrib>Ji, J.</creatorcontrib><creatorcontrib>Chuang, C.T.</creatorcontrib><creatorcontrib>Wagner, L.F.</creatorcontrib><creatorcontrib>Hsieh, C.M.</creatorcontrib><creatorcontrib>Kuang, J.B.</creatorcontrib><creatorcontrib>Hsu, L.</creatorcontrib><creatorcontrib>Pelella, M.M.</creatorcontrib><creatorcontrib>Chu, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lu, P.F.</au><au>Ji, J.</au><au>Chuang, C.T.</au><au>Wagner, L.F.</au><au>Hsieh, C.M.</au><au>Kuang, J.B.</au><au>Hsu, L.</au><au>Pelella, M.M.</au><au>Chu, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Floating body effects in partially-depleted SOI CMOS circuits</atitle><btitle>Proceedings of 1996 International Symposium on Low Power Electronics and Design</btitle><stitle>LPE</stitle><date>1996</date><risdate>1996</risdate><spage>139</spage><epage>144</epage><pages>139-144</pages><isbn>0780335716</isbn><isbn>9780780335714</isbn><abstract>This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.</abstract><pub>IEEE</pub><doi>10.1109/LPE.1996.547496</doi></addata></record> |
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| ispartof | Proceedings of 1996 International Symposium on Low Power Electronics and Design, 1996, p.139-144 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit stability Circuit topology CMOS digital integrated circuits Degradation FETs Impact ionization MOSFET circuits Semiconductor device modeling Silicon Switching circuits |
| title | Floating body effects in partially-depleted SOI CMOS circuits |
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