Floating body effects in partially-depleted SOI CMOS circuits

Floating body effects in partially-depleted SOI CMOS circuits

This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dyn...

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Hauptverfasser: Lu, P.F., Ji, J., Chuang, C.T., Wagner, L.F., Hsieh, C.M., Kuang, J.B., Hsu, L., Pelella, M.M., Chu, S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit stability
Circuit topology
CMOS digital integrated circuits
Degradation
FETs
Impact ionization
MOSFET circuits
Semiconductor device modeling
Silicon
Switching circuits
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Zusammenfassung:This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.
DOI:10.1109/LPE.1996.547496