A 622.08-Mbps Serial Data Transmitter for ATM Applications
A serial data transmitter for ATM user-network interface is described. The data transmitter gets 8-bit parallel data from SDH processor and transmits them in a serial data stream. It uses a PLL to synthesize an 8 times faster clock than the parallel data clock, which is used for serial data transmis...
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| creator | Yoo, Changsik Lee, Inyeol Yoon, Kwangho Chai, Sang-Hoon Song, Woncheol Kim, Wonchan |
| description | A serial data transmitter for ATM user-network interface is described. The data transmitter gets 8-bit parallel data from SDH processor and transmits them in a serial data stream. It uses a PLL to synthesize an 8 times faster clock than the parallel data clock, which is used for serial data transmission. To minimize bit error, the phase of the serial clock generated by the PLL is controlled by serial clock phase controller. Measured results indicate that the transmitter can operate upto 840Mbps and dissipates about 700mW at 640Mbps. The transmitter has been implemented in a 0.8μm CMOS process. |
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The data transmitter gets 8-bit parallel data from SDH processor and transmits them in a serial data stream. It uses a PLL to synthesize an 8 times faster clock than the parallel data clock, which is used for serial data transmission. To minimize bit error, the phase of the serial clock generated by the PLL is controlled by serial clock phase controller. Measured results indicate that the transmitter can operate upto 840Mbps and dissipates about 700mW at 640Mbps. The transmitter has been implemented in a 0.8μm CMOS process.</description><identifier>ISBN: 2863321803</identifier><identifier>ISBN: 9782863321805</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; CMOS technology ; Data communication ; Delay ; Frequency synthesizers ; Phase locked loops ; Shift registers ; Synchronous digital hierarchy ; Timing ; Transmitters</subject><ispartof>ESSCIRC '95: Twenty-first European Solid-State Circuits Conference, 1995, p.110-113</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5469314$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5469314$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Yoo, Changsik</creatorcontrib><creatorcontrib>Lee, Inyeol</creatorcontrib><creatorcontrib>Yoon, Kwangho</creatorcontrib><creatorcontrib>Chai, Sang-Hoon</creatorcontrib><creatorcontrib>Song, Woncheol</creatorcontrib><creatorcontrib>Kim, Wonchan</creatorcontrib><title>A 622.08-Mbps Serial Data Transmitter for ATM Applications</title><title>ESSCIRC '95: Twenty-first European Solid-State Circuits Conference</title><addtitle>ESSCIRC</addtitle><description>A serial data transmitter for ATM user-network interface is described. The data transmitter gets 8-bit parallel data from SDH processor and transmits them in a serial data stream. It uses a PLL to synthesize an 8 times faster clock than the parallel data clock, which is used for serial data transmission. To minimize bit error, the phase of the serial clock generated by the PLL is controlled by serial clock phase controller. Measured results indicate that the transmitter can operate upto 840Mbps and dissipates about 700mW at 640Mbps. The transmitter has been implemented in a 0.8μm CMOS process.</description><subject>Clocks</subject><subject>CMOS technology</subject><subject>Data communication</subject><subject>Delay</subject><subject>Frequency synthesizers</subject><subject>Phase locked loops</subject><subject>Shift registers</subject><subject>Synchronous digital hierarchy</subject><subject>Timing</subject><subject>Transmitters</subject><isbn>2863321803</isbn><isbn>9782863321805</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9ybsKwjAUANCACL76BS73Byp5tCFxCz5w6WT2cispRNI2JFn8exdnpzOcFdlxJYXgTFGxIVXOb0op01Kzlm3J2YDk_ERV3Q0xw9MljwGuWBBswjlPvhSXYFwSGNuBiTH4Fxa_zPlA1iOG7Kqfe3K83-zlUXvnXB-TnzB9-raRWrBG_N8vZV0u_g</recordid><startdate>199509</startdate><enddate>199509</enddate><creator>Yoo, Changsik</creator><creator>Lee, Inyeol</creator><creator>Yoon, Kwangho</creator><creator>Chai, Sang-Hoon</creator><creator>Song, Woncheol</creator><creator>Kim, Wonchan</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>199509</creationdate><title>A 622.08-Mbps Serial Data Transmitter for ATM Applications</title><author>Yoo, Changsik ; Lee, Inyeol ; Yoon, Kwangho ; Chai, Sang-Hoon ; Song, Woncheol ; Kim, Wonchan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_54693143</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Clocks</topic><topic>CMOS technology</topic><topic>Data communication</topic><topic>Delay</topic><topic>Frequency synthesizers</topic><topic>Phase locked loops</topic><topic>Shift registers</topic><topic>Synchronous digital hierarchy</topic><topic>Timing</topic><topic>Transmitters</topic><toplevel>online_resources</toplevel><creatorcontrib>Yoo, Changsik</creatorcontrib><creatorcontrib>Lee, Inyeol</creatorcontrib><creatorcontrib>Yoon, Kwangho</creatorcontrib><creatorcontrib>Chai, Sang-Hoon</creatorcontrib><creatorcontrib>Song, Woncheol</creatorcontrib><creatorcontrib>Kim, Wonchan</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yoo, Changsik</au><au>Lee, Inyeol</au><au>Yoon, Kwangho</au><au>Chai, Sang-Hoon</au><au>Song, Woncheol</au><au>Kim, Wonchan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 622.08-Mbps Serial Data Transmitter for ATM Applications</atitle><btitle>ESSCIRC '95: Twenty-first European Solid-State Circuits Conference</btitle><stitle>ESSCIRC</stitle><date>1995-09</date><risdate>1995</risdate><spage>110</spage><epage>113</epage><pages>110-113</pages><isbn>2863321803</isbn><isbn>9782863321805</isbn><abstract>A serial data transmitter for ATM user-network interface is described. The data transmitter gets 8-bit parallel data from SDH processor and transmits them in a serial data stream. It uses a PLL to synthesize an 8 times faster clock than the parallel data clock, which is used for serial data transmission. To minimize bit error, the phase of the serial clock generated by the PLL is controlled by serial clock phase controller. Measured results indicate that the transmitter can operate upto 840Mbps and dissipates about 700mW at 640Mbps. The transmitter has been implemented in a 0.8μm CMOS process.</abstract><pub>IEEE</pub></addata></record> |
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| identifier | ISBN: 2863321803 |
| ispartof | ESSCIRC '95: Twenty-first European Solid-State Circuits Conference, 1995, p.110-113 |
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| language | eng |
| recordid | cdi_ieee_primary_5469314 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks CMOS technology Data communication Delay Frequency synthesizers Phase locked loops Shift registers Synchronous digital hierarchy Timing Transmitters |
| title | A 622.08-Mbps Serial Data Transmitter for ATM Applications |
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