A 622.08-Mbps Serial Data Transmitter for ATM Applications

A serial data transmitter for ATM user-network interface is described. The data transmitter gets 8-bit parallel data from SDH processor and transmits them in a serial data stream. It uses a PLL to synthesize an 8 times faster clock than the parallel data clock, which is used for serial data transmis...

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Bibliographische Detailangaben
Hauptverfasser:	Yoo, Changsik, Lee, Inyeol, Yoon, Kwangho, Chai, Sang-Hoon, Song, Woncheol, Kim, Wonchan
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks CMOS technology Data communication Delay Frequency synthesizers Phase locked loops Shift registers Synchronous digital hierarchy Timing Transmitters
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Beschreibung
Zusammenfassung:	A serial data transmitter for ATM user-network interface is described. The data transmitter gets 8-bit parallel data from SDH processor and transmits them in a serial data stream. It uses a PLL to synthesize an 8 times faster clock than the parallel data clock, which is used for serial data transmission. To minimize bit error, the phase of the serial clock generated by the PLL is controlled by serial clock phase controller. Measured results indicate that the transmitter can operate upto 840Mbps and dissipates about 700mW at 640Mbps. The transmitter has been implemented in a 0.8μm CMOS process.