Implementation of processor cells for array algorithms on FPGAs

Implementation of processor cells for array algorithms on FPGAs

Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal "jigsaw tessellated" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Vassanyi, I., Erenyi, I.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Cost function
Electronics packaging
Field programmable gate arrays
Hardware
Logic arrays
Programmable logic arrays
Proposals
Systolic arrays
Tiles
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Beschreibung
Zusammenfassung:Recent advances in FPGA technology offer a suitable environment for massively parallel, fine-grain array architectures. The paper gives geometric criteria for an optimal "jigsaw tessellated" processor cell, and cost function for cell placement. The paper demonstrates the use of FPGA-based processor arrays by the implementation results of two cellular image processing algorithms. The outlined concepts are being implemented in a placement-routing tool.
ISSN:1089-6503
2376-9505
DOI:10.1109/EURMIC.1996.546364