A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC
A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 /spl mu/m to 0.3 /spl mu/m. The chip is 0...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1996-12, Vol.31 (12), p.1995-2003 |
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| Hauptverfasser: | , , , , , , , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
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| container_end_page | 2003 |
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| container_issue | 12 |
| container_start_page | 1995 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 31 |
| creator | Donnelly, K.S. Yiu-Fai Chan Ho, J.T.C. Chanh V. Tran Patel, S. Benedict Lau Jun Kim Pak Shing Chau Huang, C. Wei, J. Leung Yu Tarver, R. Kulkami, R. Stark, D. Johnson, M.G. |
| description | A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 /spl mu/m to 0.3 /spl mu/m. The chip is 0.9/spl times/3.4 mm/sup 2/ using 0.3 /spl mu/m rules. |
| doi_str_mv | 10.1109/4.545823 |
| format | Article |
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The chip is 0.9/spl times/3.4 mm/sup 2/ using 0.3 /spl mu/m rules.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.545823</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Application specific integrated circuits ; Circuit noise ; Clocks ; Delay ; Design automation ; Driver circuits ; Noise generators ; Random access memory ; Timing ; Working environment noise</subject><ispartof>IEEE journal of solid-state circuits, 1996-12, Vol.31 (12), p.1995-2003</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/545823$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/545823$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Donnelly, K.S.</creatorcontrib><creatorcontrib>Yiu-Fai Chan</creatorcontrib><creatorcontrib>Ho, J.T.C.</creatorcontrib><creatorcontrib>Chanh V. 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The chip is 0.9/spl times/3.4 mm/sup 2/ using 0.3 /spl mu/m rules.</description><subject>Application specific integrated circuits</subject><subject>Circuit noise</subject><subject>Clocks</subject><subject>Delay</subject><subject>Design automation</subject><subject>Driver circuits</subject><subject>Noise generators</subject><subject>Random access memory</subject><subject>Timing</subject><subject>Working environment noise</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1996</creationdate><recordtype>article</recordtype><sourceid/><recordid>eNp9js0KgkAYRYcoyH6gdavvBdRv1PFnaVLUQloY1E4mGWNiLJnRRW-fUNCu1eFwz-ISsqLoUIqJGzgsYLHnj4hFGYttGvmXMbEQaWwnHuKUzIy5DxoEMbXIOYUwRMg3rgH56ISueSWgEbcBSkH71B2_KgGV1FUvu6EBdHxwTaug6d3GRif6GWT5sYC0OGQLMqm5MmL55Zysd9tTtrelEKJstWy4fpWfq_7f8Q1GATrh</recordid><startdate>199612</startdate><enddate>199612</enddate><creator>Donnelly, K.S.</creator><creator>Yiu-Fai Chan</creator><creator>Ho, J.T.C.</creator><creator>Chanh V. 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The chip is 0.9/spl times/3.4 mm/sup 2/ using 0.3 /spl mu/m rules.</abstract><pub>IEEE</pub><doi>10.1109/4.545823</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1996-12, Vol.31 (12), p.1995-2003 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_545823 |
| source | IEEE Electronic Library (IEL) |
| subjects | Application specific integrated circuits Circuit noise Clocks Delay Design automation Driver circuits Noise generators Random access memory Timing Working environment noise |
| title | A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC |
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