A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC

A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC

A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 /spl mu/m to 0.3 /spl mu/m. The chip is 0...

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Veröffentlicht in:IEEE journal of solid-state circuits 1996-12, Vol.31 (12), p.1995-2003
Hauptverfasser: Donnelly, K.S., Yiu-Fai Chan, Ho, J.T.C., Chanh V. Tran, Patel, S., Benedict Lau, Jun Kim, Pak Shing Chau, Huang, C., Wei, J., Leung Yu, Tarver, R., Kulkami, R., Stark, D., Johnson, M.G.
Format: Artikel
Sprache:eng
Schlagworte:
Application specific integrated circuits
Circuit noise
Clocks
Delay
Design automation
Driver circuits
Noise generators
Random access memory
Timing
Working environment noise
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Beschreibung
Zusammenfassung:A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 /spl mu/m to 0.3 /spl mu/m. The chip is 0.9/spl times/3.4 mm/sup 2/ using 0.3 /spl mu/m rules.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.545823