A 31 ns Random Cycle VCAT-Based 4F ^ DRAM With Manufacturability and Enhanced Cell Efficiency

A functional 4F 2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with more than twice turn-on current compared with the c...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2010-04, Vol.45 (4), p.880-888
Hauptverfasser:	Song, Ki-Whan, Kim, Jin-Young, Yoon, Jae-Man, Kim, Sua, Kim, Huijung, Chung, Hyun-Woo, Kim, Hyungi, Kim, Kanguk, Park, Hwan-Wook, Kang, Hyun Chul, Tak, Nam-Kyun, Park, Dukha, Kim, Woo-Seop, Lee, Yeong-Taek, Oh, Yong Chul, Jin, Gyo-Young, Yoo, Jeihwan, Park, Donggun, Oh, Kyungseok, Kim, Changhyun, Jun, Young-Hyun
Format:	Artikel
Sprache:	eng
Schlagworte:	4F ^{2} Capacitance Capacitors cell efficiency core architecture Coupling circuits Design engineering Dielectric materials Doping DRAM Dry etching Efficiency hybrid sense-amplifier (SA) Joining processes Random access memory Scalability stack capacitor surrounding-gate vertical channel access transistor (VCAT) Wet etching
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