Advanced Ti Salicide Process for Sub-0.2 μm CMOS
Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of d...
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| creator | Rostoll, M-L. Maury, D. Regolini, J-L. Haond, M. Delpech, P. Gayet, P. LeContellec, M. |
| description | Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of direct selective TiSi2 CVD deposition on gate and S/D. We show that these techniques provide solutions for silicidation of sub-0.2 μm CMOS devices. |
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We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of direct selective TiSi2 CVD deposition on gate and S/D. We show that these techniques provide solutions for silicidation of sub-0.2 μm CMOS devices.</description><identifier>ISBN: 286332196X</identifier><identifier>ISBN: 9782863321966</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS process ; CMOS technology ; Electric resistance ; Implants ; Microelectronics ; MOSFETs ; Silicidation ; Sputter etching ; Sputtering ; Telecommunications</subject><ispartof>ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference, 1996, p.93-96</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5436226$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5436226$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Rostoll, M-L.</creatorcontrib><creatorcontrib>Maury, D.</creatorcontrib><creatorcontrib>Regolini, J-L.</creatorcontrib><creatorcontrib>Haond, M.</creatorcontrib><creatorcontrib>Delpech, P.</creatorcontrib><creatorcontrib>Gayet, P.</creatorcontrib><creatorcontrib>LeContellec, M.</creatorcontrib><title>Advanced Ti Salicide Process for Sub-0.2 μm CMOS</title><title>ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference</title><addtitle>ESSDERC</addtitle><description>Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of direct selective TiSi2 CVD deposition on gate and S/D. We show that these techniques provide solutions for silicidation of sub-0.2 μm CMOS devices.</description><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Electric resistance</subject><subject>Implants</subject><subject>Microelectronics</subject><subject>MOSFETs</subject><subject>Silicidation</subject><subject>Sputter etching</subject><subject>Sputtering</subject><subject>Telecommunications</subject><isbn>286332196X</isbn><isbn>9782863321966</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjEtqAkEUABskEDWeIJu-wMib1zM9r5cyxEQwGJhZZCf9eQ0tfsJ0IuRunsEzRTCbKmpTIzFB0kphafTno5jlvAOAW5iy0mNRLsLZHj0H2SfZ2X3yKbD8GE6ec5bxNMjuxxUwR3m9HGT7vumexEO0-8yzf09Fv3zp27divXldtYt1kQx8F40jaLAykaIFq2tuOLpgNcdQeyYCUAYMuybeAMZX6EgRMWrywSCoqXi-bxMzb7-GdLDD77aulEbU6g94mTui</recordid><startdate>199609</startdate><enddate>199609</enddate><creator>Rostoll, M-L.</creator><creator>Maury, D.</creator><creator>Regolini, J-L.</creator><creator>Haond, M.</creator><creator>Delpech, P.</creator><creator>Gayet, P.</creator><creator>LeContellec, M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>199609</creationdate><title>Advanced Ti Salicide Process for Sub-0.2 μm CMOS</title><author>Rostoll, M-L. ; Maury, D. ; Regolini, J-L. ; Haond, M. ; Delpech, P. ; Gayet, P. ; LeContellec, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-7b807249f8fa0a65e7efbda6efd5ce88003909eb7f9eb09c42b8388e268cd9203</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Electric resistance</topic><topic>Implants</topic><topic>Microelectronics</topic><topic>MOSFETs</topic><topic>Silicidation</topic><topic>Sputter etching</topic><topic>Sputtering</topic><topic>Telecommunications</topic><toplevel>online_resources</toplevel><creatorcontrib>Rostoll, M-L.</creatorcontrib><creatorcontrib>Maury, D.</creatorcontrib><creatorcontrib>Regolini, J-L.</creatorcontrib><creatorcontrib>Haond, M.</creatorcontrib><creatorcontrib>Delpech, P.</creatorcontrib><creatorcontrib>Gayet, P.</creatorcontrib><creatorcontrib>LeContellec, M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Rostoll, M-L.</au><au>Maury, D.</au><au>Regolini, J-L.</au><au>Haond, M.</au><au>Delpech, P.</au><au>Gayet, P.</au><au>LeContellec, M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Advanced Ti Salicide Process for Sub-0.2 μm CMOS</atitle><btitle>ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference</btitle><stitle>ESSDERC</stitle><date>1996-09</date><risdate>1996</risdate><spage>93</spage><epage>96</epage><pages>93-96</pages><isbn>286332196X</isbn><isbn>9782863321966</isbn><abstract>Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of direct selective TiSi2 CVD deposition on gate and S/D. We show that these techniques provide solutions for silicidation of sub-0.2 μm CMOS devices.</abstract><pub>IEEE</pub><tpages>4</tpages></addata></record> |
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| ispartof | ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference, 1996, p.93-96 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS process CMOS technology Electric resistance Implants Microelectronics MOSFETs Silicidation Sputter etching Sputtering Telecommunications |
| title | Advanced Ti Salicide Process for Sub-0.2 μm CMOS |
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