Advanced Ti Salicide Process for Sub-0.2 μm CMOS

Advanced Ti Salicide Process for Sub-0.2 μm CMOS

Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of d...

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Hauptverfasser: Rostoll, M-L., Maury, D., Regolini, J-L., Haond, M., Delpech, P., Gayet, P., LeContellec, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS process
CMOS technology
Electric resistance
Implants
Microelectronics
MOSFETs
Silicidation
Sputter etching
Sputtering
Telecommunications
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Beschreibung
Zusammenfassung:Because of the reduction of gate length and junction depth, we confirm that conventional TiSi2 formed by a 2-step RTA on sputtered Ti cannot be used for sub-0.35 μm. We have investigated new techniques using selective Si-epitaxy before sputtering Ti, and a more advanced technique that makes use of direct selective TiSi2 CVD deposition on gate and S/D. We show that these techniques provide solutions for silicidation of sub-0.2 μm CMOS devices.