Optimized Scaled LOCOS Isolation Scheme for 0.25 μm CMOS

In this paper, a scaled LOCOS isolation scheme with optimized oxidation stack and reduced field oxide thickness, is presented for 0.25 μm design rules. With this scaled LOCOS isolation technology, short bird's beak encroachment, limited field oxide thinning, high punch-trough voltage and low le...

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Hauptverfasser:	Meyssen, V.M.H., Velghe, R.M.D.A., Montree, A.H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS technology Diodes Electric breakdown Etching Furnaces Isolation technology Leakage current Oxidation Silicon Thickness measurement
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creator	Meyssen, V.M.H. Velghe, R.M.D.A. Montree, A.H.
description	In this paper, a scaled LOCOS isolation scheme with optimized oxidation stack and reduced field oxide thickness, is presented for 0.25 μm design rules. With this scaled LOCOS isolation technology, short bird's beak encroachment, limited field oxide thinning, high punch-trough voltage and low leakage current have been achieved by simple fabrication processes.
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With this scaled LOCOS isolation technology, short bird's beak encroachment, limited field oxide thinning, high punch-trough voltage and low leakage current have been achieved by simple fabrication processes.</description><identifier>ISBN: 9782863321829</identifier><identifier>ISBN: 286332182X</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS technology ; Diodes ; Electric breakdown ; Etching ; Furnaces ; Isolation technology ; Leakage current ; Oxidation ; Silicon ; Thickness measurement</subject><ispartof>ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference, 1995, p.679-682</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5436090$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5436090$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Meyssen, V.M.H.</creatorcontrib><creatorcontrib>Velghe, R.M.D.A.</creatorcontrib><creatorcontrib>Montree, A.H.</creatorcontrib><title>Optimized Scaled LOCOS Isolation Scheme for 0.25 μm CMOS</title><title>ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference</title><addtitle>ESSDERC</addtitle><description>In this paper, a scaled LOCOS isolation scheme with optimized oxidation stack and reduced field oxide thickness, is presented for 0.25 μm design rules. With this scaled LOCOS isolation technology, short bird's beak encroachment, limited field oxide thinning, high punch-trough voltage and low leakage current have been achieved by simple fabrication processes.</description><subject>CMOS technology</subject><subject>Diodes</subject><subject>Electric breakdown</subject><subject>Etching</subject><subject>Furnaces</subject><subject>Isolation technology</subject><subject>Leakage current</subject><subject>Oxidation</subject><subject>Silicon</subject><subject>Thickness measurement</subject><isbn>9782863321829</isbn><isbn>286332182X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotzMtKw0AUgOEBESo1T9DNvEDkzDVzlhK8FCKzSPflJD1DRxJTkmz02XwGn8mCrj74F_-NKLAKOnhjtAoaN6JYlncAUOhRWXcnMF7WPOYvPsm2p-FKE-vYyv0yDbTm6eOazzyyTNMs4UE7-fM9yvottvfiNtGwcPHvVhyenw71a9nEl3392JQZYS2dtYoqQujYpt53VaeNIjI-KG0rOlWQUnBEqJw3SBTYJ2DfJwpdcOjNVuz-tpmZj5c5jzR_Hp01HhDMLwJePpg</recordid><startdate>199509</startdate><enddate>199509</enddate><creator>Meyssen, V.M.H.</creator><creator>Velghe, R.M.D.A.</creator><creator>Montree, A.H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>199509</creationdate><title>Optimized Scaled LOCOS Isolation Scheme for 0.25 μm CMOS</title><author>Meyssen, V.M.H. ; Velghe, R.M.D.A. ; Montree, A.H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-5441a7a90be4fc6b7b231aa3681247ad70ff85aa915639aa8e6f0e6cfa8b85963</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>CMOS technology</topic><topic>Diodes</topic><topic>Electric breakdown</topic><topic>Etching</topic><topic>Furnaces</topic><topic>Isolation technology</topic><topic>Leakage current</topic><topic>Oxidation</topic><topic>Silicon</topic><topic>Thickness measurement</topic><toplevel>online_resources</toplevel><creatorcontrib>Meyssen, V.M.H.</creatorcontrib><creatorcontrib>Velghe, R.M.D.A.</creatorcontrib><creatorcontrib>Montree, A.H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Meyssen, V.M.H.</au><au>Velghe, R.M.D.A.</au><au>Montree, A.H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Optimized Scaled LOCOS Isolation Scheme for 0.25 μm CMOS</atitle><btitle>ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference</btitle><stitle>ESSDERC</stitle><date>1995-09</date><risdate>1995</risdate><spage>679</spage><epage>682</epage><pages>679-682</pages><isbn>9782863321829</isbn><isbn>286332182X</isbn><abstract>In this paper, a scaled LOCOS isolation scheme with optimized oxidation stack and reduced field oxide thickness, is presented for 0.25 μm design rules. With this scaled LOCOS isolation technology, short bird's beak encroachment, limited field oxide thinning, high punch-trough voltage and low leakage current have been achieved by simple fabrication processes.</abstract><pub>IEEE</pub><tpages>4</tpages></addata></record>
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language	eng
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	CMOS technology Diodes Electric breakdown Etching Furnaces Isolation technology Leakage current Oxidation Silicon Thickness measurement
title	Optimized Scaled LOCOS Isolation Scheme for 0.25 μm CMOS
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