Optimized Scaled LOCOS Isolation Scheme for 0.25 μm CMOS

Optimized Scaled LOCOS Isolation Scheme for 0.25 μm CMOS

In this paper, a scaled LOCOS isolation scheme with optimized oxidation stack and reduced field oxide thickness, is presented for 0.25 μm design rules. With this scaled LOCOS isolation technology, short bird's beak encroachment, limited field oxide thinning, high punch-trough voltage and low le...

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Bibliographische Detailangaben
Hauptverfasser: Meyssen, V.M.H., Velghe, R.M.D.A., Montree, A.H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS technology
Diodes
Electric breakdown
Etching
Furnaces
Isolation technology
Leakage current
Oxidation
Silicon
Thickness measurement
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Zusammenfassung:In this paper, a scaled LOCOS isolation scheme with optimized oxidation stack and reduced field oxide thickness, is presented for 0.25 μm design rules. With this scaled LOCOS isolation technology, short bird's beak encroachment, limited field oxide thinning, high punch-trough voltage and low leakage current have been achieved by simple fabrication processes.