Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS
An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 μm CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer LOCOS isolation scheme. Excellent thin gate oxide quality and low juncti...
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| creator | Meyssen, V. M. H. Montree, A. H. |
| description | An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 μm CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer LOCOS isolation scheme. Excellent thin gate oxide quality and low junction diode leakage are demonstrated. The feasibility of the isolation module was demonstrated in a 0.35 μm CMOS process where excellent device performance was achieved. |
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| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5435501</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5435501</ieee_id><sourcerecordid>5435501</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-1df8a81a8f0494855ee4481e68b191cbb8a66d59b71165e61946ec950cd6c8da3</originalsourceid><addsrcrecordid>eNotz0FKxDAUgOGACMrYE7jJBSp5TV76stTiqFCpMON6SJMXrbRWUl30bp7BMyk4q3_3wX8iCldTRVbrCjTimSiW5U0pBc4SQXUucJv9xFE-zeMqb75S4izbrul2cs_h9X0e55dVpjlLdaVR_nxPsnnsdhfiNPlx4eLYjXje3u6b-7Lt7h6a67YcoMbPEmIiT-ApKeMMITIbQ8CWenAQ-p68tRFdXwNYZAvOWA4OVYg2UPR6Iy7_3YGZDx95mHxeD2j-VhToX9FgPNc</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Meyssen, V. M. H. ; Montree, A. H.</creator><creatorcontrib>Meyssen, V. M. H. ; Montree, A. H.</creatorcontrib><description>An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 μm CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer LOCOS isolation scheme. Excellent thin gate oxide quality and low junction diode leakage are demonstrated. The feasibility of the isolation module was demonstrated in a 0.35 μm CMOS process where excellent device performance was achieved.</description><identifier>ISBN: 9782863321355</identifier><identifier>ISBN: 2863321358</identifier><language>eng</language><publisher>IEEE</publisher><subject>Amorphous materials ; CMOS process ; CMOS technology ; Etching ; Isolation technology ; Laboratories ; Leakage current ; Oxidation ; Scanning electron microscopy ; Silicon</subject><ispartof>ESSDERC '93: 23rd European solid State Device Research Conference, 1993, p.257-260</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5435501$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5435501$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Meyssen, V. M. H.</creatorcontrib><creatorcontrib>Montree, A. H.</creatorcontrib><title>Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS</title><title>ESSDERC '93: 23rd European solid State Device Research Conference</title><addtitle>ESSDERC</addtitle><description>An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 μm CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer LOCOS isolation scheme. Excellent thin gate oxide quality and low junction diode leakage are demonstrated. The feasibility of the isolation module was demonstrated in a 0.35 μm CMOS process where excellent device performance was achieved.</description><subject>Amorphous materials</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Etching</subject><subject>Isolation technology</subject><subject>Laboratories</subject><subject>Leakage current</subject><subject>Oxidation</subject><subject>Scanning electron microscopy</subject><subject>Silicon</subject><isbn>9782863321355</isbn><isbn>2863321358</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1993</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotz0FKxDAUgOGACMrYE7jJBSp5TV76stTiqFCpMON6SJMXrbRWUl30bp7BMyk4q3_3wX8iCldTRVbrCjTimSiW5U0pBc4SQXUucJv9xFE-zeMqb75S4izbrul2cs_h9X0e55dVpjlLdaVR_nxPsnnsdhfiNPlx4eLYjXje3u6b-7Lt7h6a67YcoMbPEmIiT-ApKeMMITIbQ8CWenAQ-p68tRFdXwNYZAvOWA4OVYg2UPR6Iy7_3YGZDx95mHxeD2j-VhToX9FgPNc</recordid><startdate>199309</startdate><enddate>199309</enddate><creator>Meyssen, V. M. H.</creator><creator>Montree, A. H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>199309</creationdate><title>Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS</title><author>Meyssen, V. M. H. ; Montree, A. H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-1df8a81a8f0494855ee4481e68b191cbb8a66d59b71165e61946ec950cd6c8da3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Amorphous materials</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Etching</topic><topic>Isolation technology</topic><topic>Laboratories</topic><topic>Leakage current</topic><topic>Oxidation</topic><topic>Scanning electron microscopy</topic><topic>Silicon</topic><toplevel>online_resources</toplevel><creatorcontrib>Meyssen, V. M. H.</creatorcontrib><creatorcontrib>Montree, A. H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Meyssen, V. M. H.</au><au>Montree, A. H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS</atitle><btitle>ESSDERC '93: 23rd European solid State Device Research Conference</btitle><stitle>ESSDERC</stitle><date>1993-09</date><risdate>1993</risdate><spage>257</spage><epage>260</epage><pages>257-260</pages><isbn>9782863321355</isbn><isbn>2863321358</isbn><abstract>An advanced isolation method, Framed Poly-Buffer LOCOS (FPBLOCOS), for a 0.35 μm CMOS technology is presented in this paper. The bird's beak length of the FPBLOCOS isolation technique is smaller compared to the Poly Buffer LOCOS isolation scheme. Excellent thin gate oxide quality and low junction diode leakage are demonstrated. The feasibility of the isolation module was demonstrated in a 0.35 μm CMOS process where excellent device performance was achieved.</abstract><pub>IEEE</pub><tpages>4</tpages></addata></record> |
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| ispartof | ESSDERC '93: 23rd European solid State Device Research Conference, 1993, p.257-260 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Amorphous materials CMOS process CMOS technology Etching Isolation technology Laboratories Leakage current Oxidation Scanning electron microscopy Silicon |
| title | Framed Poly Buffer LOCOS Technology for 0.35 μm CMOS |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T20%3A04%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Framed%20Poly%20Buffer%20LOCOS%20Technology%20for%200.35%20%CE%BCm%20CMOS&rft.btitle=ESSDERC%20'93:%2023rd%20European%20solid%20State%20Device%20Research%20Conference&rft.au=Meyssen,%20V.%20M.%20H.&rft.date=1993-09&rft.spage=257&rft.epage=260&rft.pages=257-260&rft.isbn=9782863321355&rft.isbn_list=2863321358&rft_id=info:doi/&rft_dat=%3Cieee_6IE%3E5435501%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5435501&rfr_iscdi=true |