A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS

A 567 mm 2 processor on 45 nm CMOS integrates 48 IA-32 cores and 4 DDR3 channels in a 6×4 2D-mesh network. Cores communicate through message passing using 384 KB of on-die shared memory. Fine-grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of co...

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Hauptverfasser: Howard, J., Dighe, S., Hoskote, Y., Vangal, S., Finan, D., Ruhl, G., Jenkins, D., Wilson, H., Borkar, N., Schrom, G., Pailet, F., Jain, S., Jacob, T., Yada, S., Marella, S., Salihundam, P., Erraguntla, V., Konow, M., Riepen, M., Droege, G., Lindemann, J., Gries, M., Apel, T., Henriss, K., Lund-Larsen, T., Steibl, S., Borkar, S., De, V., Van Der Wijngaart, R., Mattson, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS process
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Beschreibung
Zusammenfassung:A 567 mm 2 processor on 45 nm CMOS integrates 48 IA-32 cores and 4 DDR3 channels in a 6×4 2D-mesh network. Cores communicate through message passing using 384 KB of on-die shared memory. Fine-grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. As performance scales, the processor dissipates between 25 W and 125 W.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5434077