A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 ¿W from...

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Bibliographische Detailangaben
Hauptverfasser: Harpe, P., Cui Zhou, Xiaoyan Wang, Dolmans, G., de Groot, H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
CMOS logic circuits
Energy consumption
Frequency measurement
Inverters
Parasitic capacitance
Power measurement
Sampling methods
Switched capacitor networks
Switches
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Beschreibung
Zusammenfassung:An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 ¿W from a 1 V supply. The corresponding FoM equals 30 fJ/Conversion-step and is maintained down to 10 kS/s.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5433967