A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O

A dual-PLL system for 45 nm SOI-CMOS processors is designed to clock a multi-protocol wireline I/O for high-speed digital communications covering a frequency range from 1 GHz up to 11.1 GHz. The two PLLs, based on a ring and LC-tank VCO, achieve .99 ps and 0.55 ps rms jitter, respectively. Circuit a...

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Bibliographische Detailangaben
Hauptverfasser: Fischette, D.M., Loke, A.L.S., Oshima, M.M., Doyle, B.A., Bakalski, R., DeSantis, R.J., Thiruvengadam, A., Wang, C.L., Talbot, G.R., Fang, E.S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Circuit noise
Clocks
Filters
Frequency
Jitter
Phase locked loops
Regulators
Voltage
Voltage-controlled oscillators
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Beschreibung
Zusammenfassung:A dual-PLL system for 45 nm SOI-CMOS processors is designed to clock a multi-protocol wireline I/O for high-speed digital communications covering a frequency range from 1 GHz up to 11.1 GHz. The two PLLs, based on a ring and LC-tank VCO, achieve .99 ps and 0.55 ps rms jitter, respectively. Circuit and architectural techniques to minimize the impact of SOI floating-body effect on phase jitter are introduced.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5433942