A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique

A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique

A 10 b pipelined ADC employs opamp and time-sharing techniques to reduce the power consumption and silicon area. The presented ADC needs only one opamp to complete the 10 b conversion. The chip is fabricated in a 90 nm digital CMOS process and occupies 0.058 mm 2 . It operates at 100 MS/S and achiev...

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Bibliographische Detailangaben
Hauptverfasser: Yen-Chuan Huang, Tai-Cheng Lee
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Calibration
Circuits
Clocks
CMOS technology
Degradation
Energy consumption
Frequency
Power generation
Threshold voltage
Time sharing computer systems
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Beschreibung
Zusammenfassung:A 10 b pipelined ADC employs opamp and time-sharing techniques to reduce the power consumption and silicon area. The presented ADC needs only one opamp to complete the 10 b conversion. The chip is fabricated in a 90 nm digital CMOS process and occupies 0.058 mm 2 . It operates at 100 MS/S and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0 V supply.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5433927