A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

A 90 nm 256 Kb NAND-ROM using read-1 noise elimination and read-0 sensing-margin-expanding schemes is functional at 0.29 V and 3 MHz with 100% code-coverage and 5% area overhead. This work reduces the delay-per-BL-length, energy-per-bit at V DDmin , and V DDmin -delay-product by 3000×, 4× and 3700×,...

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Hauptverfasser: Meng-Fan Chang, Shu-Meng Yang, Chih-Wei Liang, Chih-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Yamauchi, H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitors
CMOS memory circuits
CMOS process
Crosstalk
Decision support systems
Feedback circuits
Laser sintering
Nonvolatile memory
Read only memory
Voltage
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Beschreibung
Zusammenfassung:A 90 nm 256 Kb NAND-ROM using read-1 noise elimination and read-0 sensing-margin-expanding schemes is functional at 0.29 V and 3 MHz with 100% code-coverage and 5% area overhead. This work reduces the delay-per-BL-length, energy-per-bit at V DDmin , and V DDmin -delay-product by 3000×, 4× and 3700×, respectively, compared to previous low-voltage ROMs.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5433914