A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor

A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor

The POWER7 TM microprocessor features a 32 kB L1 data cache with a 2R and banked-1W functionality using a 6T-SRAM cell. Read/write collision is intercepted inside the array with write-over-read priority. The array-specific power supply improves SRAM cell stability and performance while reducing the...

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Bibliographische Detailangaben
Hauptverfasser: Pille, J., Wendel, D., Wagner, O., Sautter, R., Penth, W., Froehnel, T., Buettner, S., Torreiter, O., Eckert, M., Paredes, J., Hrusecky, D., Ray, D., Canada, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
Energy consumption
Frequency
Hardware
Logic arrays
Logic devices
Random access memory
Stability
Voltage control
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Beschreibung
Zusammenfassung:The POWER7 TM microprocessor features a 32 kB L1 data cache with a 2R and banked-1W functionality using a 6T-SRAM cell. Read/write collision is intercepted inside the array with write-over-read priority. The array-specific power supply improves SRAM cell stability and performance while reducing the logic voltage level. The macro is fabricated in a 45nm CMOS SOI technology.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2010.5433849