Throughput optimization for interleaved repeater-inserted interconnects in VLSI design

This paper presents analytical modeling and closed-form derivations for the throughput of interleaved repeater-inserted resistive-capacitive global interconnects in VLSI design. We have used interleaved buffer insertion technique which has been well-accepted to be dominated in minimization of crosstalk effects in current nanometer technologies. Moreover, we have used the simple yet-realistic MOS model, namely the ¿-power law, to consider the input transition time in the throughput expression. Precise HSPICE simulations have been used to verify the analytical throughput derivations.