Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor

Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor

This paper presents the implementation of Advanced Audio and Video Standard Part 2: Video (AVS P2), the Chinese video standard, to Diamond 388VDO Video Processor, a heterogeneous dual core Tensilica SIMD processor. Through the process of mapping AVS video decoder to 388VDO we aim to explore and expl...

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Hauptverfasser: Koziri, M., Bellas, N., Katsavounidis, I., Zacharis, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Communication standards
Decoding
Delay
Engines
High definition video
Parallel processing
Random access memory
Read-write memory
Streaming media
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Bellas, N.
Katsavounidis, I.
Zacharis, D.
description This paper presents the implementation of Advanced Audio and Video Standard Part 2: Video (AVS P2), the Chinese video standard, to Diamond 388VDO Video Processor, a heterogeneous dual core Tensilica SIMD processor. Through the process of mapping AVS video decoder to 388VDO we aim to explore and exploit the different forms of parallelism inherent in a video application in order to speedup AVS decoding and achieve real time functionality.
doi_str_mv 10.1109/ICCE.2010.5418696
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5418696</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5418696</ieee_id><sourcerecordid>5418696</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-92c56cd1a6bdeab12bd187048056c6ece93038fcd623d836f8d74793cd01fd9d3</originalsourceid><addsrcrecordid>eNo1kM1OAjEUhesPiYg8gHHTFxjsz51OuyQj6iQYFxC3pPTekTFASWcw8e2ZKJ7NyTlfchaHsXspJlIK91iV5WyiRB9zkNY4c8FuJSgA0NLAJRsqmdsMhJBXbOwK-8-guD4z7RwM2NBCZn77GzZu2y_RC3JlbDFki2p32NKO9p3vmrjnsebdhvj0Y8G_G6TIkUJESrxnnm-ooxQ_aU_x2HI8-m0WYiK-qN6e-CHFQG0b0x0b1H7b0vjsI7Z8ni3L12z-_lKV03nWONFlToXcBJTerJH8Wqo1SlsIsKKvDQVyWmhbBzRKo9WmtlhA4XRAIWt0qEfs4W-2IaLVITU7n35W56v0CadQVmg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Koziri, M. ; Bellas, N. ; Katsavounidis, I. ; Zacharis, D.</creator><creatorcontrib>Koziri, M. ; Bellas, N. ; Katsavounidis, I. ; Zacharis, D.</creatorcontrib><description>This paper presents the implementation of Advanced Audio and Video Standard Part 2: Video (AVS P2), the Chinese video standard, to Diamond 388VDO Video Processor, a heterogeneous dual core Tensilica SIMD processor. Through the process of mapping AVS video decoder to 388VDO we aim to explore and exploit the different forms of parallelism inherent in a video application in order to speedup AVS decoding and achieve real time functionality.</description><identifier>ISSN: 2158-3994</identifier><identifier>ISBN: 9781424443147</identifier><identifier>ISBN: 1424443148</identifier><identifier>EISSN: 2158-4001</identifier><identifier>EISBN: 1424443164</identifier><identifier>EISBN: 9781424443161</identifier><identifier>DOI: 10.1109/ICCE.2010.5418696</identifier><identifier>LCCN: 84-643147</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Communication standards ; Decoding ; Delay ; Engines ; High definition video ; Parallel processing ; Random access memory ; Read-write memory ; Streaming media</subject><ispartof>2010 Digest of Technical Papers International Conference on Consumer Electronics (ICCE), 2010, p.267-268</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5418696$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2057,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5418696$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Koziri, M.</creatorcontrib><creatorcontrib>Bellas, N.</creatorcontrib><creatorcontrib>Katsavounidis, I.</creatorcontrib><creatorcontrib>Zacharis, D.</creatorcontrib><title>Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor</title><title>2010 Digest of Technical Papers International Conference on Consumer Electronics (ICCE)</title><addtitle>ICCE</addtitle><description>This paper presents the implementation of Advanced Audio and Video Standard Part 2: Video (AVS P2), the Chinese video standard, to Diamond 388VDO Video Processor, a heterogeneous dual core Tensilica SIMD processor. Through the process of mapping AVS video decoder to 388VDO we aim to explore and exploit the different forms of parallelism inherent in a video application in order to speedup AVS decoding and achieve real time functionality.</description><subject>Clocks</subject><subject>Communication standards</subject><subject>Decoding</subject><subject>Delay</subject><subject>Engines</subject><subject>High definition video</subject><subject>Parallel processing</subject><subject>Random access memory</subject><subject>Read-write memory</subject><subject>Streaming media</subject><issn>2158-3994</issn><issn>2158-4001</issn><isbn>9781424443147</isbn><isbn>1424443148</isbn><isbn>1424443164</isbn><isbn>9781424443161</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kM1OAjEUhesPiYg8gHHTFxjsz51OuyQj6iQYFxC3pPTekTFASWcw8e2ZKJ7NyTlfchaHsXspJlIK91iV5WyiRB9zkNY4c8FuJSgA0NLAJRsqmdsMhJBXbOwK-8-guD4z7RwM2NBCZn77GzZu2y_RC3JlbDFki2p32NKO9p3vmrjnsebdhvj0Y8G_G6TIkUJESrxnnm-ooxQ_aU_x2HI8-m0WYiK-qN6e-CHFQG0b0x0b1H7b0vjsI7Z8ni3L12z-_lKV03nWONFlToXcBJTerJH8Wqo1SlsIsKKvDQVyWmhbBzRKo9WmtlhA4XRAIWt0qEfs4W-2IaLVITU7n35W56v0CadQVmg</recordid><startdate>201001</startdate><enddate>201001</enddate><creator>Koziri, M.</creator><creator>Bellas, N.</creator><creator>Katsavounidis, I.</creator><creator>Zacharis, D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201001</creationdate><title>Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor</title><author>Koziri, M. ; Bellas, N. ; Katsavounidis, I. ; Zacharis, D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-92c56cd1a6bdeab12bd187048056c6ece93038fcd623d836f8d74793cd01fd9d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Clocks</topic><topic>Communication standards</topic><topic>Decoding</topic><topic>Delay</topic><topic>Engines</topic><topic>High definition video</topic><topic>Parallel processing</topic><topic>Random access memory</topic><topic>Read-write memory</topic><topic>Streaming media</topic><toplevel>online_resources</toplevel><creatorcontrib>Koziri, M.</creatorcontrib><creatorcontrib>Bellas, N.</creatorcontrib><creatorcontrib>Katsavounidis, I.</creatorcontrib><creatorcontrib>Zacharis, D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Koziri, M.</au><au>Bellas, N.</au><au>Katsavounidis, I.</au><au>Zacharis, D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor</atitle><btitle>2010 Digest of Technical Papers International Conference on Consumer Electronics (ICCE)</btitle><stitle>ICCE</stitle><date>2010-01</date><risdate>2010</risdate><spage>267</spage><epage>268</epage><pages>267-268</pages><issn>2158-3994</issn><eissn>2158-4001</eissn><isbn>9781424443147</isbn><isbn>1424443148</isbn><eisbn>1424443164</eisbn><eisbn>9781424443161</eisbn><abstract>This paper presents the implementation of Advanced Audio and Video Standard Part 2: Video (AVS P2), the Chinese video standard, to Diamond 388VDO Video Processor, a heterogeneous dual core Tensilica SIMD processor. Through the process of mapping AVS video decoder to 388VDO we aim to explore and exploit the different forms of parallelism inherent in a video application in order to speedup AVS decoding and achieve real time functionality.</abstract><pub>IEEE</pub><doi>10.1109/ICCE.2010.5418696</doi><tpages>2</tpages></addata></record>
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subjects Clocks
Communication standards
Decoding
Delay
Engines
High definition video
Parallel processing
Random access memory
Read-write memory
Streaming media
title Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T17%3A15%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Implementation%20of%20the%20AVS%20video%20decoder%20on%20a%20heterogeneous%20dual-core%20SIMD%20processor&rft.btitle=2010%20Digest%20of%20Technical%20Papers%20International%20Conference%20on%20Consumer%20Electronics%20(ICCE)&rft.au=Koziri,%20M.&rft.date=2010-01&rft.spage=267&rft.epage=268&rft.pages=267-268&rft.issn=2158-3994&rft.eissn=2158-4001&rft.isbn=9781424443147&rft.isbn_list=1424443148&rft_id=info:doi/10.1109/ICCE.2010.5418696&rft_dat=%3Cieee_6IE%3E5418696%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424443164&rft.eisbn_list=9781424443161&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5418696&rfr_iscdi=true