Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor

Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor

This paper presents the implementation of Advanced Audio and Video Standard Part 2: Video (AVS P2), the Chinese video standard, to Diamond 388VDO Video Processor, a heterogeneous dual core Tensilica SIMD processor. Through the process of mapping AVS video decoder to 388VDO we aim to explore and expl...

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Bibliographische Detailangaben
Hauptverfasser: Koziri, M., Bellas, N., Katsavounidis, I., Zacharis, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Communication standards
Decoding
Delay
Engines
High definition video
Parallel processing
Random access memory
Read-write memory
Streaming media
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Beschreibung
Zusammenfassung:This paper presents the implementation of Advanced Audio and Video Standard Part 2: Video (AVS P2), the Chinese video standard, to Diamond 388VDO Video Processor, a heterogeneous dual core Tensilica SIMD processor. Through the process of mapping AVS video decoder to 388VDO we aim to explore and exploit the different forms of parallelism inherent in a video application in order to speedup AVS decoding and achieve real time functionality.
ISSN:2158-3994
2158-4001
DOI:10.1109/ICCE.2010.5418696