Efficient FPGA implementation for the IEEE 802.16e interleaver

In this paper, we implement and evaluate a novel design for the hardware of the multi-mode interleaver block used in the OFDMA mode of the IEEE 802.16e (Mobile WiMAX) standard. A new architecture that is both area and delay efficient is introduced. The area and delay efficiency of this new architecture is verified via quantitative comparisons between FPGA implementations of this architecture and classical interleaver designs.