Design of an optimized SRM control architecture based on a hardware/software partitioning
This paper presents an effective digital speed control implementation for a switched reluctance machine. An optimized architecture is proposed based on a hardware/software partitioning in order to implement it on a System on Programmable Chip. This solution leads to a user-friendly development solut...
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| creator | Hilairet, M. Hannoun, H. Marchand, C. |
| description | This paper presents an effective digital speed control implementation for a switched reluctance machine. An optimized architecture is proposed based on a hardware/software partitioning in order to implement it on a System on Programmable Chip. This solution leads to a user-friendly development solution without over pending for performance or sacrificing features. Finally, the proposed strategy achieves lower current and torque ripples in a large speed range compared to a software implementation. |
| doi_str_mv | 10.1109/IECON.2009.5415107 |
| format | Conference Proceeding |
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An optimized architecture is proposed based on a hardware/software partitioning in order to implement it on a System on Programmable Chip. This solution leads to a user-friendly development solution without over pending for performance or sacrificing features. Finally, the proposed strategy achieves lower current and torque ripples in a large speed range compared to a software implementation.</description><subject>Application software</subject><subject>Computer architecture</subject><subject>continuous and discontinuous conduction mode</subject><subject>Costs</subject><subject>Design optimization</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>Hardware</subject><subject>hardware/software partitioning</subject><subject>Reluctance machines</subject><subject>Reluctance motors</subject><subject>speed control</subject><subject>Switched reluctance machine</subject><subject>System on Programmable Chip</subject><subject>Torque control</subject><subject>Velocity control</subject><issn>1553-572X</issn><isbn>9781424446483</isbn><isbn>1424446481</isbn><isbn>9781424446506</isbn><isbn>9781424446490</isbn><isbn>1424446503</isbn><isbn>142444649X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpNUMtKAzEUjahgqfMDuskPTJubx2SylLFqoVrwAboqmcxNG2lnSiYi-vWO2IVncR4cOItDyAWwCQAz0_msWj5MOGNmoiQoYPqIZEaXILmUslCsOP6fZSlOyAiUErnS_PWMZH3_zgZIBZqZEXm7xj6sW9p5agfep7AL39jQp8d76ro2xW5LbXSbkNClj4i0tv1Qdy21dGNj82kjTvvOp19D9zamkELXhnZ9Tk693faYHXRMXm5mz9VdvljezqurRR5Aq5TXnpeuZo0AtJbXDj3numwKhEIUHJwGVlpde6eammutLRpj0BQl84Jzo8WYXP7tBkRc7WPY2fi1OpwjfgBpA1bh</recordid><startdate>200911</startdate><enddate>200911</enddate><creator>Hilairet, M.</creator><creator>Hannoun, H.</creator><creator>Marchand, C.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200911</creationdate><title>Design of an optimized SRM control architecture based on a hardware/software partitioning</title><author>Hilairet, M. ; Hannoun, H. ; Marchand, C.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-bf28cb0d31eaa2bcef2278d6e163621c7108a7bfc5db2777ae999e9680f322973</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Application software</topic><topic>Computer architecture</topic><topic>continuous and discontinuous conduction mode</topic><topic>Costs</topic><topic>Design optimization</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>Hardware</topic><topic>hardware/software partitioning</topic><topic>Reluctance machines</topic><topic>Reluctance motors</topic><topic>speed control</topic><topic>Switched reluctance machine</topic><topic>System on Programmable Chip</topic><topic>Torque control</topic><topic>Velocity control</topic><toplevel>online_resources</toplevel><creatorcontrib>Hilairet, M.</creatorcontrib><creatorcontrib>Hannoun, H.</creatorcontrib><creatorcontrib>Marchand, C.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hilairet, M.</au><au>Hannoun, H.</au><au>Marchand, C.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design of an optimized SRM control architecture based on a hardware/software partitioning</atitle><btitle>2009 35th Annual Conference of IEEE Industrial Electronics</btitle><stitle>IECON</stitle><date>2009-11</date><risdate>2009</risdate><spage>4053</spage><epage>4057</epage><pages>4053-4057</pages><issn>1553-572X</issn><isbn>9781424446483</isbn><isbn>1424446481</isbn><eisbn>9781424446506</eisbn><eisbn>9781424446490</eisbn><eisbn>1424446503</eisbn><eisbn>142444649X</eisbn><abstract>This paper presents an effective digital speed control implementation for a switched reluctance machine. An optimized architecture is proposed based on a hardware/software partitioning in order to implement it on a System on Programmable Chip. This solution leads to a user-friendly development solution without over pending for performance or sacrificing features. Finally, the proposed strategy achieves lower current and torque ripples in a large speed range compared to a software implementation.</abstract><pub>IEEE</pub><doi>10.1109/IECON.2009.5415107</doi><tpages>5</tpages></addata></record> |
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| identifier | ISSN: 1553-572X |
| ispartof | 2009 35th Annual Conference of IEEE Industrial Electronics, 2009, p.4053-4057 |
| issn | 1553-572X |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Application software Computer architecture continuous and discontinuous conduction mode Costs Design optimization Field programmable gate arrays FPGA Hardware hardware/software partitioning Reluctance machines Reluctance motors speed control Switched reluctance machine System on Programmable Chip Torque control Velocity control |
| title | Design of an optimized SRM control architecture based on a hardware/software partitioning |
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